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NTE21256 262,144-Bit Dynamic Random Access Memory (DRAM)
Description: The NTE21256 is a 262,144 word by 1-bit dynamic Random Access Memory. This 5V-only component is fabricated with N-channel silicon gate technology. Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard 16-Lead DIP package. Features of this device include single power supply with 10% tolerance, on- chip address, date registers which eliminate the need for interface registers, and fully TTL compatible inputs and outputs, including clocks. In addition to the usual read, write, and read-modify-write cycles, the NTE21256 is capable of early and late write cycles, RAS-only refresh, and hidden refresh. Common I/O capability is given by using early write operation. The NTE21256 also features page mode which allows high-speed random access of bits in the same row. Features: D 262,144 x 1-Bit Organization D Single +5V Supply, 10% Tolerance D Low Power Dissipation: -385mW active (Max) -28mW standby (Max) D Access Time: 150ns D Cycle Time: 260ns D All Inputs and Outputs TTL Compatible D On-Chip Substrate Bias Generator D Three-State Data Output D Read, Write, Read-Modify-Write, RAS-Only-Refresh, Hidden Refresh D Common I/O Capability using "Early Write" Operation D Page Mode Read and Write, Read-Write D 256 Refresh Cycles with 4ms Refresh Period Absolute Maximum Ratings: (Note 1) Operating Temperature Range, Topr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Voltage on any pin relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 to +7V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Data Out Current (Short Circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Note 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Functional Description: Device Initialization Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required. For power-up, an initial pause of 200s is necessary for the internal bias generator to establish the proper substrate bias voltage. To initialize the nodes of the dynamic circuitry, a minimum of 8 active cycles of the Row Address Strobe (RAS) has to be performed. This is also necessary after an extended inactive state of greater than 4ms. Addressing (A0-A8) For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row Address bits are set up on pins A0 through A8 and latched into the row address latches by the Row Address Strobe (RAS). Then the 9 column address bits are set up on pins A0 through A8 and latched into the column address latches by the Column Address Strobe (CAS). All input addresses must be stable on the falling edges of RAS and CAS. It should be noted that RAS is similar to a Chip Enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and the input and output buffers. Write Enable (WE) The read or write mode is selected with the WE input. A logic high (VIH) on WE dictates read mode; logic low (VIL) dictates write mode. The data input is disabled when read mode is selected. When WE goes low prior to CAS, data output (DO) will remain in the high-impedance state for the entire cycle permitting common I/O operation. Data Input (DI) Data is written during a write or read-modify-write cycle. The falling edge of CAS or WE strobes data into the on-chip data latch. In an early write cycle, WE is brought low prior to CAS and the data is strobed in by CAS with setup and hold times referenced to this signal. Data Output (DO) The output is three-state TTL compatible with a fan-out of two standard TTL loads. Data Out has the same polarity as Data In. The output is in a high impedance state until CAS is brought low. In a read cycle or read-write cycle, the output is valid after tRAC from transition of RAS when tRCD (Min) is satisfied, or after tCAC from transition of CAS when the transition occurs after tRCD (Max). In an early write cycle, the output is always in the high impedance state. In a delayed write or read-modify-write cycle, the output will follow the sequence for the read cycle. With CAS going high the output returns to the high impedance state within tOFF. Hidden Refresh RAS-only refresh cycle may take place while maintaining valid output data. This feature is referred to as Hidden Refresh. Hidden Refresh is performed by holding CAS at VIL of a previous memory read cycle. Refresh Cycle A refresh operation must be performed at least every 4ms to retain data. Since the output buffer is in the high impedance state unless CAS is applied, the RAS-only refresh sequence avoids any signal during refresh. Strobing each of the 256 row addresses (A0 through A7) with RAS, causes all bits in each row to be refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power. Page Mode Page-mode operation allows effectively faster memory access by maintaining the row address and strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe sequential row addresses for the same page is no longer required. The maximum number of columns that can be addressed in sequence is determined by tRAS, the maximum RAS low pulse width.
DC Characteristics: (TA = 0 to +70C, VSS = 0V, VCC = +5V 10% unless otherwise specified)
Parameter Input High Voltage (All Inputs) Input Low Voltage (All Inputs) Output High Voltage Output Low Voltage Average VCC Supply Current Standby VCC Supply Current Average VCC Supply Current during RAS-only refresh cycles Average VCC supply Current during Page Mode Input Leakage Current (Any Input) Output Leakage Current Supply Voltage Symbol VIH VIL VOH VOL ICC1 ICC2 ICC3 ICC4 II (L) IO (L) VCC VSS CAS at Logic 1, 0 V out 5.5 Note 2 Test Conditions Notes 2, Note3 Notes 2, Note3 Note 4 Note 5 tRC = 260ns, Note 6 Note 7 Note 6 Note 6 Min 2.4 -1.0 2.4 - - - - - - - 4.5 0 Typ - - - - - - - - - - - - Max VCC +1 0.8 - 0.4 70 5 65 55 10 10 5.5 0 Unit V V V V mA mA mA mA A A V V
Note 2. All voltages referenced to VSS. Note 3. Overshooting and undershooting on input levels of +6.5V or -2V for a period 0f 30ns Max. will influence function and reliability of the device. Note 4. IOH = 4mA and 100pf load. Note 5. IOL = 4mA and 100pf load. Note 6. ICC depends on frequency of operation. Maximum current is measured at the fastest cycle rate. Note 7. RAS and CAS are both at VIH.
Capacitance: (Note 6)
Parameter Input Capacitance (A0-A8, DI) Input Capacitance (RAS, CAS, WE) Output Capacitance (DO, CAS = VIH to disable output) Symbol CI1 CI2 CO Test Conditions Min - - - Typ - - - Max Unit 6 7 7 pF pF pF
Note 6. Effective capacitance calculated from the equation: C= I * t with V = 3V or measured with Boonton meter. V
AC Test Conditions: Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns between 0.8 and 2.4V Input Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 to 2.4V Output Timing Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.4 to 2.4V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . equivelent to 2 standard TTL loads and 100pf
AC Characteristics: (TA = 0 to +70C, VCC = 5V 10%, Note 9, Note 10, Note 11 unless otherwise specified)
Parameter Random Read or Write Cycle Time Read-Modify-Write Cycle Time Access Time from RAS Access Time from CAS RAS Pulse Width CAS Pulse Width Refresh Period RAS Precharge Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS Hold Time CAS Hold Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time referenced to RAS Transition Time (Rise and Fall) Read Command Setup Time Read Command Hold Time referenced to CAS Read Command Hold Time referenced to RAS Output Buffer Turn-Off Delay Symbol tRC tRWC tRAC tCAC tRAS tCAS tREF tRP tCRP tRCD tRSH tCSH tASR tRAH tASC tCAH tAR tT tRCS tRCH tRRH tOFF Note 18 Note 18 Note 19 Note 17 Note 9 Note 16 Test Conditions Note 12 Note 12 Notes 13, Note 14 Notes 13, Note 15 Min 260 310 - - 150 75 - 100 0 30 75 150 0 20 0 30 105 3 0 0 10 0 Typ - - - - - - - - - - - - - - - - - - - - - - Max Unit - - 150 75 104 - 4 - - 75 - - - - - - - 50 - - - 40 ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 9. VIH and VIL are reference levels to measure timing of input signals. Also, transition times are measured between VIH and VIL. Note10. An initial pause of 200s is required after power-up followed by a minimum of eight initialization cycles prior to normal operation. Note 11. The time parameters specified here are valid for a transition time of tT = 5ns for the input signals Note12. The specification for tRC (Min), tRWC (Min), and page-mode cycle time (tPC) are only used to indicate cycle time at which proper operation over full temperature range (0C TA +70C) is assured. Note13. Measured with a load equivalent to two TTL loads and 100pf. Note14. Assumes that tRCD tRCD (Max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. Note15. Assumes that tRCD tRCD (Max). Note16. Operation within the tRCD (Max) limit ensures that tRAC (Max) can be met. tRCD (Max) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max) limit, then access time is controlled exclusively by tCAC. Note17. tRCD + tCAH tAR Min, tRCD + tDH tDHR Min, tRCD + tWCH tWCR Min. Note18. Either tRRH or tRCH must be satisfied for a read cycle. Note19. tOFF (Max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
AC Characteristics (Cont'd): (TA = 0 to +70C, VCC = 5V 10%, Note 9, Note 10, Note 11 unless otherwise specified)
Parameter Write Command Setup Time Write Command Hold Time Write Command Hold Time referenced to RAS Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data in Setup Time Data in Hold Time Data in Hold Time referenced to RAS CAS to WE Delay RAS to WE Delay RMW Cycle RAS Pulse Width RMW Cycle CAS Pulse Width Page Mode Cycle Time Page Mode Read-Write Cycle Time Page Mode CAS Precharge Time Symbol tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tCWD tRWD tRRW tCRW tPC tPRWC tCP Note 12 Note 21 Note 21 Note 17 Note 20 Note 20 Note 17 Test Conditions Note 20 Min 0 45 120 45 45 45 0 45 120 75 150 200 125 145 190 60 Typ - - - - - - - - - - - - - - - - Max Unit - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 9. VIH and VIL are reference levels to measure timing of input signals. Also, transition times are measured between VIH and VIL. Note10. An initial pause of 200s is required after power-up followed by a minimum of eight initialization cycles prior to normal operation. Note 11. The time parameters specified here are valid for a transition time of tT = 5ns for the input signals Note12. The specification for tRC (Min), tRWC (Min), and page-mode cycle time (tPC) are only used to indicate cycle time at which proper operation over full temperature range (0C TA +70C) is assured. Note17. tRCD + tCAH tAR Min, tRCD + tDH tDHR Min, tRCD + tWCH tWCR Min. Note20. tWCS, tCWD, and tRWC are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: If tWCS tWCS (Min), the cycle is an early write cycle and the Data Out will remain open circuit (high impedance) throughout the entire cycle; if tCWD tCWD (Min) and tRWD tRWD (Min) the cycle is a read-write cycle and the Data Out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the Data Out (at access time) is indeterminate. Note21. tDS and tDH are referenced to the leading edge of CAS in early write cycles, and to the leading edge of WE in delayed write of read-modify-write cycles.
Pin Connection Diagram
A8 1 DI 2 WE 3 RAS 4 A0 5 A2 6 A1 7 VCC 8
16 VSS 15 CAS 14 DO 13 A6 12 A3 11 A4 10 A5 9 A7
16
9 .260 (6.6) Max
1
8
.785 (19.9) Max .200 (5.08) Max .245 (6.22) Min
.300 (7.62)
.100 (2.54) .700 (17.7)

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